Understanding and addressing performance issues in HEP
                            Sverre Jarp/CERN 

Chapter 1. Definition of the HEP hardware/compiler phase space:

         - CPU specifications (frequency, microarchitectural features),
           multicore designs, cache sizes, bus speeds, chip sets, 
           I/O rates, etc.

         - Compilers (versions, features, flags, etc.). The compilers' 
           encounters with the application software, algorithms, 
           programming style, advanced C++ features, etc.

Chapter 2. Review of performance tools (hardware/software)

Chapter 3. Illustration of measurements inside the HEP phase space with a 
           few of the most relevant HEP applications, in three forms:

         a) Software kernels (testing only one feature at a time)

         b) Well-known ROOT, GEANT4 test jobs (with emphasis on one HEP 
            feature, such as tracking in detector geometries, etc.)

         c) Full LHC application (such as G4ATLAS, ALIROOT, etc.)